This invention relates generally to a high speed complimentary metal oxide semiconductor (HCMOS) decoder circuit and, more particularly, to a high speed HCMOS decoder which will permit logic operation at voltages greater than the breakdown voltages inherent in the semiconductor manufacturing process.
While typically a CMOS circuit will break down at, for example, 18 volts, occasionally it is necessary to operate such a circuit at voltages higher than the breakdown voltage. For example, non-volatile memories (e.g. EPROMS and EEPROMS) require a high programming voltage which, in the past, has been limited by the gate-aided junction breakdown (i.e. the drain-to-substrate breakdown voltage with the gate shorted to the source). These higher programming voltages are necessary to achieve satisfactory program and erase times. Gate induced electric fields inherent in the HCMOS process further aggravate the breakdown problem in that a field-effect-transistor (FET) in its off state may be subject to maximum chip voltage.